1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more specifically to a semiconductor device having so-called power semiconductor elements such as a power transistor, a rectifying element and the like and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A surface mounted type semiconductor device can be mounted securely and easily on a mounting substrate (printed circuit board), on which a wiring pattern is formed, by a solder reflow method, a flow method or the like and has advantages that it is compact, light and excellent in reliability.
Conventionally, a power semiconductor element such as a power transistor (for example, power MOSFET) has a so-called vertical structure in which two main electrodes, a source electrode 51 and a drain electrode 52, are disposed on both the surfaces of a semiconductor chip 53 as shown in FIG. 18. And, a semiconductor device on which the vertical type semiconductor element is mounted is configured that an electrode (e.g., the source electrode 51), which is not directly bonded to a wiring pattern 55 of a mounting substrate (printed circuit board) 54, is connected to a source side wiring pattern 55 via a bonding wire 56.
As a compact and thin semiconductor device excelling in heat dissipation, there is proposed a semiconductor device which is configured by disposing a metallic lead frame on a resin layer which is formed to cover a semiconductor chip, and exposing the end surface of an electrode terminal which is extracted from the semiconductor chip via the lead frame and the surface of the electrode of the semiconductor chip on the plane surface of the mounting surface (e.g., Japanese Patent Laid-Open Application No. 2003-086737).
In addition, there is proposed as a chip scale surface mounted device a semiconductor device having a structure that a metallic clip or cap of a copper alloy or the like is bonded instead of a bonding wire to a semiconductor chip by a conductive adhesive (e.g., U.S. Pat. No. 6,767,820).
But, the above semiconductor devices have a decrease in efficiency of the circuit because they have a high wire resistance or inductance. In addition, they have an increase in mounting area depending on the lead frame or cap. Therefore, sufficient miniaturization could not be achieved. And, the semiconductor device described in U.S. Pat. No. 6,767,820 had a disadvantage that its cost was high because the used material cost was high.
An object of the present invention is to provide a semiconductor device which is thin and compact in size, low in current path resistance and parasitic inductance and excellent in reliability; and a method of manufacturing such a highly reliable semiconductor device.